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connection diagram 8-pin plastic mini-dip (n), cerdip (q) and soic (r) packages ?n ref g=10/100 g=10/100 +in output ? s +v s 1 2 3 4 8 7 6 5 top view AD621 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low drift, low power instrumentation amplifier AD621 features easy to use pin-strappable gains of 10 & 100 all errors specified for total system performance higher performance than discrete in-amp designs available in 8-pin dip and soic low power, 1.3 ma max supply current wide power supply range ( 6 2.3 v to 6 18 v) excellent dc performance 0.15% max, total gain error 6 5 ppm/ 8 c, total gain drift 125 m v max, total offset voltage 1.0 m v/ 8 c max, offset voltage drift low noise 9 nv/ ? hz , @ 1 khz, input voltage noise 0.28 m v p-p noise (0.1 hz to 10 hz} excellent ac specifications 800 khz bandwidth (g = 10}, 200 khz (g = 100} 12 m s settling time to 0.01% applications weigh scales transducer interface & data acquisition systems industrial process controls battery powered and portable equipment one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product description the AD621 is an easy to use, low cost, low power, high accu- racy instrumentation amplifier which is ideally suited for a wide range of applications. its unique combination of high perfor- mance, small size and low power, outperforms discrete in amp implementations. high functionality, low gain errors and low gain drift errors are achieved by the use of internal gain setting resistors. fixed gains of 10 and 100 can be easily set via external 30,000 15,000 20,000 25,000 10,000 5,000 0 5 10 15 20 total error, ppm of full scale supply current ?ma AD621a 3 - op amp in-amps (3 op 07's) three op amp ia designs vs. AD621 pin strapping. the AD621 is fully specified as a total system, therefore, simplifying the design process. for portable or remote applications, where power dissipation, size and weight are critical, the AD621 features a very low sup- ply current of 1.3 ma max and is packaged in a compact 8-pin soic, 8-pin plastic dip or 8-pin cerdip. the AD621 also excels in applications requiring high total accuracy, such as pre- cision data acquisition systems used in weigh scales and trans- ducer interface circuits. low maximum error specifications including nonlinearity of 10 ppm, gain drift of 5 ppm/ c, 50 m v offset voltage and 0.6 m v/ c offset drift (b grade), make pos- sible total system performance at a lower cost than has been pre- viously achieved with discrete designs or with other monolithic instrumentation amplifiers. when operating from high source impedances, as in ecg and blood pressure monitors, the AD621 features the ideal combina- tion of low noise and low input bias currents. voltage noise is specified as 9 nv/ ? hz at 1 khz and 0.28 m v p-p from 0.1 hz to 10 hz. input current noise is also extremely low at 0.1 pa/ ? hz . the AD621 outperforms fet input devices with an input bias current specification of 1.5 na max over the full industrial tem- perature range. 10,000 1,000 100 10 1 0.1 1k 10k 100k 1m 10m 100m source resistance ? w total input voltage noise, g = 100 ? m vp-p (0.1 ?10hz) AD621 super?ta bipolar input in-amp typical standard bipolar input in-amp total voltage noise vs. source resistance
AD621Cspecifications gain = 10 AD621a AD621b ad620s 1 model conditions min typ max min typ max min typ max units gain gain error v out = 10 v 0.15 0.05 0.15 % nonlinearity, v out = C10 v to +10 v r l = 2 k w 2 10 2 10 2 10 ppm of fs gain vs. temperature C1.5 5 C1.5 5C1 5 ppm/ c total voltage offset offset (rti) v s = 15 v 75 250 50 125 75 250 m v over temperature v s = 5 v to 15 v 400 215 500 m v average tc v s = 5 v to 15 v 1.0 2.5 0.6 1.5 1.0 2.5 m v/ c offset referred to the input vs. supply (psr) 2 v s = 2.3 v to 18 v 95 120 100 120 95 120 db total noise voltage noise (rti) 1 khz 13 17 13 17 13 17 nv/ ? hz rti 0.1 hz to 10 hz 0.55 0.55 0.8 0.55 0.8 m v p-p current noise f = 1 khz 100 100 100 fa/ ? hz 0.1 hzC10 hz 10 10 10 pa p-p input current v s = 15 v input bias current 0.5 2.0 0.5 1.0 0.5 2 na over temperature 2.5 1.5 4 na average tc 3.0 3.0 8.0 pa/ c input offset current 0.3 1.0 0.3 0.5 0.3 1.0 na over temperature 1.5 0.75 2.0 na average tc 1.5 1.5 8.0 pa/ c input input impedance differential 10 i 210 i 210 i 2g w i pf common-mode 10 i 210 i 210 i 2g w i pf input voltage range 3 v s = 2.3 v to 5 v Cv s + 1.9 +v s C 1.2 Cv s + 1.9 +v s C 1.2 Cv s + 1.9 +v s C 1.2 v over temperature Cv s + 2.1 +v s C 1.3 Cv s + 2.1 +v s C 1.3 Cv s + 2.1 +v s C 1.3 v v s = 5 v to l8 v Cv s + 1.9 +v s C 1.4 Cv s + 1.9 +v s C 1.4 Cv s + 1.9 +v s C 1.4 v over temperature Cv s + 2.1 +v s C 1.4 Cv s + 2.1 +v s C 1.4 Cv s + 2.3 +v s C 1.4 v common-mode rejection ratio dc to 60 hz with 1 k w source imbalance v cm = 0 v to 10 v 93 110 100 110 93 110 db output output swing r l = 10 k w , v s = 2.3 v to 5 v Cv s + 1.1 +v s C 1.2 Cv s + 1.1 +v s C 1.2 Cv s + 1.1 +v s C 1.2 v over temperature Cv s + 1.4 +v s C 1.3 Cv s + 1.4 +v s C 1.3 Cv s + 1.6 +v s C 1.3 v v s = 5 v to 18 v Cv s + 1.2 +v s C 1.4 Cv s + 1.2 +v s C 1.4 Cv s + 1.2 +v s C 1.4 v over temperature Cv s + 1.6 +v s C 1.5 Cv s + 1.6 +v s C 1.5 Cv s + 2.3 +v s C 1.5 v short current circuit 18 18 18 ma dynamic response small signal, C3 db bandwidth 800 800 800 khz slew rate 0.75 1.2 0.75 1.2 0.75 1.2 v/ m s settling time to 0.01% 10 v step 12 12 12 m s reference input r in 20 20 20 k w i in v in +, v ref = 0 +50 +60 +50 +60 +50 +60 m a voltage range Cv s + 1.6 +v s C 1.6 Cv s + 1.6 +v s C 1.6 v s + 1.6 +v s C 1.6 v gain to output 1 0.0001 1 0.0001 1 0.0001 power supply operating range 2.3 18 2.3 18 2.3 18 v quiescent current v s = 2.3 v to 18 v 0.9 1.3 0.9 1.3 0.9 1.3 ma over temperature 1.1 1.6 1.1 1.6 1.1 1.6 ma temperature range for specified performance C40 to +85 C40 to +85 C55 to +125 c notes 1 see analog devices military data sheet for 883b tested specifications. 2 this is defined as the supply range over which psrr is defined. 3 input voltage range = cmv + (gain v diff ). specifications subject to change without notice. (typical @ +25 8 c, v s = 6 15 v, and r l = 2 k v , unless otherwise noted) rev. a C2C
AD621a AD621b ad620s 1 model conditions min typ max min typ max min typ max units gain gain error v out = 10 v 0.15 0.05 0.15 % nonlinearity, v out = C10 v to +10 v r l = 2 k w 2 10 2 10 2 10 ppm of fs gain vs. temperature C1 5C1 5C1 5 ppm/ c total voltage offset offset (rti) v s = 15 v 35 125 25 50 35 125 m v over temperature v s = 5 v to 15 v 185 215 225 m v average tc v s = 5 v to 15 v 0.3 1.0 0.1 0.6 0.3 1.0 m v/ c offset referred to the input vs. supply (psr) 2 v s = 2.3 v to 18 v 110 140 120 140 110 140 db total noise voltage noise (rti) 1 khz 9 13 9 13 9 13 nv/ ? hz rti 0.1 hz to 10 hz 0.28 0.28 0.4 0.28 0.4 m v p-p current noise f = 1 khz 100 100 100 fa/ ? hz 0.1 hzC10 hz 10 10 10 pa p-p input current v s = 15 v input bias current 0.5 2.0 0.5 1.0 0.5 2 na over temperature 2.5 1.5 4 na average tc 3.0 3.0 8.0 pa/ c input offset current 0.3 1.0 0.3 0.5 0.3 1.0 na over temperature 1.5 0.75 2.0 na average tc 1.5 1.5 8.0 pa/ c input input impedance differential 10 i 210 i 210 i 2g w i pf common-mode 10 i 210 i 210 i 2g w i pf input voltage range 3 v s = 2.3 v to 5 v Cv s + 1.9 +v s C 1.2 Cv s + 1.9 +v s C 1.2 Cv s + 1.9 +v s C 1.2 v over temperature Cv s + 2.1 +v s C 1.3 Cv s + 2.1 +v s C 1.3 Cv s + 2.1 +v s C 1.3 v v s = 5 v to l8 v Cv s + 1.9 +v s C 1.4 Cv s + 1.9 +v s C 1.4 Cv s + 1.9 +v s C 1.4 v over temperature Cv s + 2.1 +v s C 1.4 Cv s + 2.1 +v s C 1.4 Cv s + 2.3 +v s C 1.4 v common-mode rejection ratio dc to 60 hz with 1 k w source imbalance v cm = 0 v to 10 v 110 130 120 130 110 130 db output output swing r l = 10 k w , v s = 2.3 v to 5 v Cv s + 1.1 +v s C 1.2 Cv s + 1.1 +v s C 1.2 Cv s + 1.1 +v s C 1.2 v over temperature Cv s + 1.4 +v s C 1.3 Cv s + 1.4 +v s C 1.3 Cv s + 1.6 +v s C 1.3 v v s = 5 v to 18 v Cv s + 1.2 +v s C 1.4 Cv s + 1.2 +v s C 1.4 Cv s + 1.2 +v s C 1.4 v over temperature Cv s + 1.6 +v s C 1.5 Cv s + 1.6 +v s C 1.5 Cv s + 2.3 +v s C 1.5 v short current circuit 18 18 18 ma dynamic response small signal, C3 db bandwidth 200 200 200 khz slew rate 0.75 1.2 0.75 1.2 0.75 1.2 v/ m s settling time to 0.01% 10 v step 12 12 12 m s reference input r in 20 20 20 k w i in v in +, v ref = 0 +50 +60 +50 +60 +50 +60 m a voltage range Cv s + 1.6 +v s C 1.6 Cv s + 1.6 +v s C 1.6 v s + 1.6 +v s C 1.6 v gain to output 1 0.0001 1 0.0001 1 0.0001 power supply operating range 2.3 18 2.3 18 2.3 18 v quiescent current v s = 2.3 v to 18 v 0.9 1.3 0.9 1.3 0.9 1.3 ma over temperature 1.1 1.6 1.1 1.6 1.1 1.6 ma temperature range for specified performance C40 to +85 C40 to +85 C55 to +125 c notes 1 see analog devices military data sheet for 883b tested specifications. 2 this is defined as the supply range over which psee is defined. 3 input voltage range = cmv + (gain v diff ). specifications subject to change without notice. gain = 100 (typical @ +25 8 c, v s = 6 15 v, and r l = 2 k v , unless otherwise noted) AD621 rev. a C3C
AD621 rev. a C4C notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-pin plastic package: q ja = 95 c/watt 8-pin cerdip package: q ja = 110 c/watt 8-pin soic package: q ja = 155 c/watt absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . . 650 mw input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 25 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite storage temperature range (q) . . . . . . . . . . C65 c to +150 c storage temperature range (n, r) . . . . . . . . C65 c to +125 c operating temperature range AD621 (a, b) . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c AD621 (s) . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300 c esd susceptibility esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without de- tection. although the AD621 features proprietary esd protec- tion circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic dis- charges. therefore, proper esd precautions are recommended to avoid any performance degradation or loss of functionality. ordering guide temperature package package model range description option 1 AD621an C 40 c to +85 c 8-pin plastic dip n-8 AD621bn C 40 c to +85 c 8-pin plastic dip n-8 AD621ar C 40 c to +85 c 8-pin plastic soic r-8 AD621br C 40 c to +85 c 8-pin plastic soic r-8 AD621sq/883b 2 C55 c to +125 c 8-pin cerdip q-8 AD621achips C40 c to +85 c die notes 1 n = plastic dip; q = cerdip; r = soic. 2 see analog devices' military data sheet for 883b specifications. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions.
typical characteristicsCAD621 50 0 ?00 10 30 20 40 +200 +100 0 ?00 input offset voltage ? m v percentage of units sample size = 90 figure 1. typical distribution of v os, gain = 10 50 0 ?0 10 30 20 40 +80 +40 0 ?0 input offset voltage ? m v percentage of units sample size = 90 figure 2. typical distribution of v os , gain = 100 50 0 ?00 10 30 20 40 +400 +200 0 ?00 input offset current ?pa percentage of units sample size = 90 figure 3. typical distribution of input offset current 50 0 ?00 10 30 20 40 +800 +400 0 ?00 input bias current ?pa percentage of units sample size = 90 figure 4. typical distribution of input bias current change in offset voltage ? m v 1.5 0.5 warm-up time ?minutes 2 0 05 1 1 4 3 2 figure 5. change in input offset voltage vs. warm-up time 1 10 100 1k frequency ?hz 1 10 100 1000 10k 100k voltage noise ?nv/ ? hz gain = 10 gain = 100 figure 6. voltage noise spectral density rev. a C5C
AD621 rev. a C6C frequency ?hz 1000 100 10 1 10 1000 100 current noise ?fa/ hz figure 7. current noise spectral density vs. frequency rti noise ?0.2 m v/div time ?1 sec/div figure 8a. 0.1 hz to 10 hz rti voltage noise, gain = 10 rti noise ?0.1 m v/div time ?1 sec/div figure 8b. 0.1 hz to 10 hz rti voltage noise, g = 100 10 90 100 0% 100mv 1s figure 9. 0.1 hz to 10 hz current noise, 5 pa per vertical div, 1 second per horizontal div 100 1000 AD621a fet input in-amp source resistance ? w total drift from 25 c to 85 c, rti ? m v 100,000 10 1k 10m 10,000 10k 1m 100k figure 10. total drift vs. source resistance 10 100 1k 10k 100k 1m frequency ?hz 1 0.1 0 +20 +40 +60 +80 +100 +120 +140 cmr ?db +160 gain = 100 gain = 10 figure 11. cmr vs. frequency, rti, for a zero to 1 k w source imbalance
AD621 rev. a C7C frequency ?hz psr ?db 160 1m 80 40 1 60 0.1 140 100 120 100k 10k 1k 100 10 20 g = 100 g = 10 180 figure 12. positive psr vs. frequency frequency ?hz psr ?db 160 1m 80 40 1 60 0.1 140 100 120 100k 10k 1k 100 10 20 g = 100 g = 10 180 figure 13. negative psr vs. frequency 1000 100 10m 100 1 1k 10 100k 1m 10k frequency ?hz closed-loop gain ?v/v 0.1 figure 14. closed-loop gain vs. frequency output voltage ?volts p-p frequency ?hz 35 0 1m 15 5 10k 10 1k 30 20 25 100k g = 10 & 100 figure 15. large signal frequency response input voltage limit ?volts (referred to supply voltages) 20 +1.0 +0.5 5 0 +1.5 ?.5 ?.0 ?.5 15 10 supply voltage volts +v s ? s ?.0 +0.0 figure 16. input voltage range vs. supply voltage 20 +1.0 +0.5 5 0 +1.5 ?.5 ?.0 ?.5 15 10 supply voltage volts r = 10k w l r = 2k w l r = 10k w l +v s ? s output voltage swing ?volts (referred to supply voltages) ?.0 +0.0 r = 2k w l figure 17. output voltage swing vs. supply voltage, g = 10
AD621 rev. a C8C output voltage swing ?volts p-p load resistance ? w 30 0 0 10k 20 10 100 1k g = 10 v = 15v s figure 18. output voltage swing vs. resistive load 10 90 100 0% 1mv 5v 10 m s figure 19. large signal pulse response and settling time gain, g = 10 (0.5 mv = 0.01%), r l = 1 k w , c l = 100 pf 10 90 100 0% 20mv 10 m s figure 20. small signal pulse response, g = 10, r l = 1 k w , c l = 100 pf 10 90 100 0% 1mv 5v 10 m s 10 figure 21. large signal pulse response and settling time, g = 100 (0.5 mv = 0.1%), r l = 2 k w , c l = 100 pf 10 90 100 0% 20mv 10 m s figure 22. small signal pulse response, g = 100, r l = 2 k w , c l = 100 pf output step size ?volts settling time ? m s to 0.01% to 0.1% 20 0 020 15 5 5 10 10 15 figure 23. settling time vs. step size, g = 10
AD621 rev. a C9C output step size ?volts settling time ? m s to 0.01% to 0.1% 20 0 020 15 5 5 10 10 15 figure 24. settling time vs. step size, gain = 100 temperature ? c input current ?na +i b ? b 2.0 ?.0 175 ?.0 ?.5 ?5 ?.5 0 0.5 1.0 1.5 125 75 25 ?5 ?25 figure 25. input bias current vs. temperature 10 90 100 0% 0 wfm 0pw 0 20 wfm aqr warning 2v vzr 0 100 m v figure 26. gain nonlinearity, g = 100, r l = 10 k w , c l = 0 pf. vertical scale: 100 m v/div = 100 ppm/div horizontal scale: 2 volts/div 10 90 100 0% 2v 100 m v figure 27. gain nonlinearity, g = 10, r l = 10 k w , vertical scale: 100 m v/div = 100 ppm/div, horizontal scale: 2 volts/div AD621 v out 10k w 1k w 10k w g=10 3 8 1 2 4 6 7 +v s 11k w 1k w 0.1% 0.1% 100k w 0.1% input 20v p-p ? s 5 g=100 g=10 1% 10t 1% g=100 figure 28. settling time test circuit
AD621 rev. a C10C v b ? s a1 a2 a3 c2 q1 q2 25k r3 400 w 10k w 10k w i2 i1 10k w ref 10k w +in ?in 20 m a 20 m a r4 400 w output c1 25k 5555.6 w 555.6 w g=100 g=100 +v s 1 8 4 2 3 6 5 7 r1 r2 r5 r6 figure 29. simplified schematic of AD621 theory of operation the AD621 is a monolithic instrumentation amplifier based on a modification of the classic three op amp circuit. careful layout of the chip, with particular attention to thermal symmetry builds in tight matching and tracking of critical components, thus pre- serving the high level of performance inherent in this circuit, at a low price. on chip gain resistors are pretrimmed for gains of 10 and 100. the AD621 is preset to a gain of 10. a single external jumper (between pins 1 and 8) is all that is needed to select a gain of 100. special design techniques assure a low gain tc of 5 ppm/ c max, even at a gain of 100. figure 29 is a simplified schematic of the AD621. the input transistors q1 and q2 provide a single differential-pair bipolar input for high precision, yet offer 10 lower input bias current, thanks to super b eta processing. feedb ack through the q1-a1-r1 loop and the q2-a2-r2 loop maintains constant collector cur- rent of the input devices q1 and q2, thereby impressing the input voltage across the gain-setting resistor, rg, which equals r5 at a gain of 10 or the parallel combination of r5 and r6 at a gain of 100. this creates a differential gain from the inputs to the a1/a2 outputs given by g = (r1 + r2) / rg + 1. the unity-gain sub- tracter a3 removes any common-mode signal, yielding a single- ended output referred to the ref pin potential. the value of rg also determines the transconductance of the preamp stage. as rg is reduced for larger gains, the transcon- ductance increases asymptotically to that of the input transis- tors. this has three important advantages: (a) open-loop gain is boosted for increasing programmed gain, thus reducing gain-re- lated errors. (b) the gain-bandwidth product (determined by c1, c2 and the preamp transconductance) increases with pro- grammed gain, thus optimizing frequency response. (c) the in- put voltage noise is reduced to a value of 9 nv/ ? hz , determined mainly by the collector current and base resistance of the input devices. make vs. buy: a typical bridge application error budget the AD621 offers improved performance over discrete three op amp ia designs, along with smaller size, fewer components and 10 times lower supply current. in the typical application, shown in figure 30, a gain of 100 is required to amplify a bridge out- put of 20 mv full scale over the industrial temperature range of C40 c to +85 c. the error budget table below shows how to calculate the effect various error sources have on circuit accuracy. regardless of the system it is being used in, the AD621 provides greater accuracy, and at low power and price. in simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. in more complex systems with an intelli- gent processor, an auto-gain/auto-zero cycle will remove all ab- solute accuracy and drift errors leaving only the resolution errors of gain nonlinearity and noise, thus allowing full 14-bit accuracy. note that for the discrete circuit, the op07 specifications for in- put voltage offset and noise have been multiplied by 2. this is because a three op amp type in amp has two op amps at its in- puts, both contributing to the overall input error. r = 350 w +10v precision bridge transducer AD621a monolithic instrumentation amplifier, g=100 3 op-amp in-amp, g=100 *0.02% resistor match, 3ppm/ c tracking **discrete 1% resistor, 100ppm/ c tracking supply current = 15ma max 100 w ** 10k w * 10k w ** 10k w * 10k w * 10k w ** 10k w * supply current = 1.3ma max op07d op07d op07d AD621a reference r = 350 w r = 350 w r = 350 w figure 30. make vs. buy
AD621 rev. a C11C 3k +5v digital data output adc ref in agnd 20k 10k 20k AD621b 1.7ma 1.3ma max 0.10ma 0.6ma max 3k 3k 3k 4 ad705 2 1 8 3 7 6 5 figure 31. a pressure monitor circuit which operates on a +5 v power supply pressure measurement although useful in many bridge applications such as weigh- scales, the AD621 is especially suited for higher resistance pres- sure sensors powered at lower voltages where small size and low power become more even significant. figure 31 shows a 3 k w pressure transducer bridge powered from +5 v. in such a circuit, the bridge consumes only 1.7 ma. adding the AD621 and a buffered voltage divider allows the sig- nal to be conditioned for only 3.8 ma of total supply current. small size and low cost make the AD621 especially attractive for voltage output pressure transducers. since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasion blood pressure measurement. wide dynamic range gain block suppresses la rge common- mode and offset signals the AD621 is especially useful in wide dynamic range applica- tions such as those requiring the amplification of signals in the presence of large, unwanted common-mode signals or offsets. many monolithic in amps achieve low total input drift and noise errors only at relatively high gains (~100). in contrast the AD621s low output errors allow such performance at a gain of 10, thus allowing larger input signals and therefore greater dynamic range. the circuit of figure 32 ( 15 v supply, g = 10) has only 2.5 m v/ c max. v os drift and 0.55 m /v p-p typical 0.1 hz to 10 hz noise, yet will amplify a 0.5 v differential sig- nal while suppressing a 10 v common-mode signal, or it will amplify a 1.25 v differential signal while suppressing a 1 v offset by use of the dac driving the reference pin of the AD621. an added benefit, the offsetting dac connected to the reference pin allows removal of a dc signal without the associ- ated time-constant of ac coupling. note the representations of a differential and common-mode signal shown in figure 32 such that a single-ended (or normal mode) signal of +1 v would be composed of a +0.5 v common-mode component and a +1 v differential component. table i. make vs. buy error budget AD621 circuit discrete circuit error, ppm of full scale error source calculation calculation AD621 discrete absolute accuracy at t a = +25 c input offset voltage, m v 125 m v/20 mv (150 m v 2 /20 mv 1 6,250 15,000 output offset voltage, m v n/a ((150 m v 2)/100)/20 mv n/a 12, 150 input offset current, na 2 na 350 w /20 mv (6 na 350 w )/20 mv 12,1 18 121, 53 cmr, db 110 db ? 3.16 ppm, 5 v/20 mv (0.02% match 5 v)/20 mv 12, 791 1 4,988 total absolute error 1 7,558 20,191 drift to +85 c gain drift, ppm/ c 5 ppm 60 c 100 ppm/ c track 60 c 13, 300 12, 600 input offset voltage drift, m v/ c1 m v/ c 60 c/20 mv (2.5 m v/ c 2 60 c)/20 mv 1 3,000 15,000 output offset voltage drift, m v/ c n/a (2.5 m v/ c 2 60 c)/100/20 mv n/a 12, 150 total drift error 1 3,690 15,750 resolution gain nonlinearity, ppm of full scale 40 ppm 40 ppm 12,1 40 12,1 40 typ 0.1 hzC10 hz voltage noise, m v p-p 0.28 m v p-p/20 mv (0.38 m v p-p ? 2 )120 mv 121, 14 12,1 27 total resolution error 121, 54 121, 67 grand total error 11,472 36,008 g = 100, v s = 15 v. (all errors are min/max and referred to input.)
AD621 rev. a C12C ad548 1 8 6 5 3 2 x10 AD621 dac 0 to 10v 1 8 6 5 3 2 x10 AD621 10k w 10k w v out2 total gain = 100 optional v diff 0.5v input a: 10v cm v com 10v + + v diff + v offset (1.25v + 1v) input b: 1v offset + v out1 6 3 2 to ref c r to v out1 use this in place of the dac for zero suppression function. g = 10 figure 32. suppressing a large common-mode or offset voltage in order to measure a small differential signal (v s = 15 v) the AD621, as well as many other monolithic instrumentation amplifiers, is based on the three op amp in amp circuit (fig- ure 33) amplifier. since the input amplifiers (a1 and a2) have a c ommon-mode gain of unity and a differential gain equal to the set gain of the overall in amp, the voltages v1 and v2 are de- fined by the equations v 1 = v cm + g v diff /2 v 2 = v cm C g v diff /2 the common-mode voltage will drive the outputs of amplifiers a1 and a2 to the differential-signal voltage, multiplied by the gain, spreads them apart. for a +10 v common-mode +0.1 v differential input, v1 would be at +10.5 v and v2 at +9.5 v. a1 a2 a3 4.44k w 20k w 20k w v1 10k w v2 10k w 10k w 10k w input amplifier output amplifier differential gain = 10 common mode gain = 1 differential gain = 1 common mode gain = 1/1000 figure 33. typical three op amp instrumentation amplifier, differential gain = 10 the AD621s input amplifiers can provide output voltage within 2.5 v of the supplies. to avoid saturation of the input amplifier the input voltage must therefore obey the equations: v cm + g v diff / 2 ( upper supply C 2.5 v ) v cm C g v diff / 2 3 ( lower supply + 2.5 v ) figure 34 shows the trade-off between common-mode and differential-mode input for 15 v supplies and g = 10. by cascading with use of the optional AD621, the circuit of fig- ure 32 will provide 1 v of zero suppression at gains of 10 and 100 (at v out1 and v out2 respectively) with maximum tcs of 4 ppm/ c and 8 ppm/ c, respectively. therefore, depending on the magnitude of the differential input signal, either v out1 or v out2 may be used as the output. 0 0.2 0 0.6 0.4 1.0 1.2 0.8 12 10 6 4 2 8 v diff ?volts ?volts v cm figure 34. trade-off between v cm and v diff range (v s = 15 v, g = 10), for reference pin at ground
AD621 rev. a C13C precision v-i converter the AD621 along with another op amp and two resistors make a precision current source (figure 35). the op amp buffers the reference terminal to maintain good cmr. the output voltage v x of the AD621 appears across r1 which converts it to a cur- rent. this current less only the input bias current of the op amp then flows out to the load. AD621 +v s ? s v in+ v in ad705 load r1 i l v x i = l r1 = in+ (v ) ?(v ) g in r1 3 7 6 5 4 2 + v x figure 35. precision voltage to current converter (operates on 1.8 ma, 3 v) input and output offset voltage the AD621 is fully specified for total input errors at gains of 10 and 100. that is, effects of all error sources within the AD621 are properly included in the guaranteed input error specs, elimi- nating the need for separate error calculation. total error rti = input error + ( output error/g ) total error rto = (input error g) + output error reference terminal although usually grounded, the reference terminal may be used to offset the output of the AD621. this is useful when the load is floating or does not share a ground with the rest of the sys- tem. it also provides a direct means of injecting a precise offset. another benefit of having a reference terminal is that it can be quite effective in eliminating ground loops and noise in a circuit or system. 7 4 6 5 3 2 AD621 r p r p v ou t v ol v ol gain = 10 or 100 +v s ? s figure 36. input overload protection input overload considerations failure of a transducer, faults on input lines, or power supply sequencing can subject the inputs of an instrumentation ampli- fier to voltages well beyond their linear range, or even the supply voltage, so it is essential that the amplifier handle these over- loads without being damaged. the AD621 will safely withstand continuous input overloads of 3.0 volts ( 6.0 ma). this is true for gains of 10 and 100, with power on or off. the inputs of the AD621 are protected by high current capacity dielectrically isolated 400 w thin-film resistors r3 and r4 (fig- ure 29) and by diodes which protect the input transistors q1 and q2 from reverse breakdown. if reverse breakdown occurred, there would be a permanent increase in the amplifiers input current. the input overload capability of the AD621 can be easily in- creased while only slightly degrading the noise, common-mode rejection and offset drift of the device by adding external resis- tors in series with the amplifiers inputs as shown in figure 36. table ii summarizes the overload voltages and total input noise for a range of range of r values. note that a 2 k w resistor in se- ries with each input will protect the AD621 from a 15 volt continuous overload, while only increasing input noise to 13 nv ? hz about the same level as would be expected from a typical unprotected 3 op amp in amp. table ii. input overload protection vs. value of resistor r p total input noise maximum continuous value of in nv ? hz @ 1 khz overload voltage, v ol resistor r p g = 10 g = 100 in volts 01493 499 w 14 10 6 1.00 k w 14 11 9 2.00 k w 15 13 15 3.01 k w *16 14 21 4.99 k w *17 16 33 *1/4 watt, 1% metal-film resistor. all others are 1/8 watt, 1% rn55 or equivalent.
AD621 rev. a C14C gain selection the AD621 has accurate, low temperature coefficient (tc), gains of 10 and 100 available. the gain of the AD621 is nomi- nally set at 10; this is easily changed to a gain of 100 by simply connecting a jumper between pins 1 and 8. 6 5 3 2 AD621 r ext 555.5 w 5,555.5 w ... ... figure 37. programming the AD621 for gains between 10 and 100 as shown in figure 37, the device can be programmed for any gain between 10 and 100 by connecting a single external resistor between pins 1 and 8. note that adding the external resistor will degrade both the gain accuracy and gain tc. since the gain equation of the AD621 yields: g = 1 + 9( r x + 6,111.111) ( r x + 555.555) this can be solved for the nominal value of external resistor for gains between 10 and 100: r x = ( g 1) 555.555 55,000 (10 g ) table iii gives practical 1% resistor values for several common gains. table iii. practical 1% external resistor values for gains between 10 and 100 desired recommended gain error temperature gain 1% resistor value coefficient (tc) 10 (pins 1 and 8 open) * *5 ppm/ c max 20 4.42 k ? 10% ? 0.4 (50 ppm/ c + resistor tc) 50 698 w? 10% ? 0.4 (50 ppm/ c + resistor tc) 100 0 (pins 1 and 8 shorted)* *5 ppm/ c max a high performance programmable gain amplifier the excellent performance of the AD621 at a gain of 10 make it a good choice to team up with the ad526 programmable gain amplifier (pga) to yield a differential input pga with gains of 10, 20, 40, 80, 160. as shown in figure 38, the low offset of the AD621 allows total circuit offset to be trimmed using the offset null of the ad526, with only a negligible increase in total drift error. the total gain tc will be 9 ppm/ c max, with 2 m v/ c typical input offset drift. bandwidth is 600 khz to gains of 10 to 80, and 350 khz at g = 160. settling time is 13 m s to 0.01% for a 10 v output step for all gains. 7 4 6 5 3 2 AD621 +v s ? s inputs + 10 7 9 4 3 ad526 +v s ? s 0.1 m f 0.1 m f g = 10 8 5 6 0.1 m f output 2 20k w offset null (optional) 0.1 m f figure 38. a high performance programmable gain amplifier common-mode rejection instrumentation amplifiers like the AD621 offer high cmr which is a measure of the change in output voltage when both inputs arc changed by equal amounts. these specifications are usually given for a full-range input voltage change and a speci- fied source imbalance. for optimal cmr the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. in many applications shielded cables are used to minimize noise, and for best cmr over frequency the shield should he properly driven. figures 39 and 40 show active data guards which are configured to improve ac common-mode rejections by bootstrapping the capacitances of input cable shields, thus minimizing the capaci- tance mismatch between the inputs. reference v out AD621 100 w 100 w ?input + input ad648 1 2 3 7 8 5 6 4 +v s ? s 100k w 100k w ? s figure 39. differential shield driver, g = 10 ad548 100 w ?input + input reference v out AD621 4 ? s +v s 8 3 1 2 7 5 6 figure 40. common-mode shield driver, g = 100
AD621 rev. a C15C grounding since the AD621 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the ref pin to the appropriate local ground. in order to isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (figure 41). it would be conve- nient to use a single ground line; however, current through ground wires and pc runs of the circuit card can cause hun- dreds of millivolts of error. therefore, separate ground returns should be provided to minimize the current flow from the sensi- tive points to the system ground. these ground returns must be tied together at some point, usually best at the adc package as shown. digital p.s. +5v c analog p.s. +15v c ?5v ad574a digital data output + 1 m f AD621 0.1 m f ad585 s/h adc 3 5 9 11 15 6 2 4 7 1 11 7 6 4 0.1 m f 1 m f1 m f figure 41. basic grounding practice ground returns for input bias currents input bias currents are those currents necessary to bias the input transistors of an amplifier. there must be a direct return path for these currents; therefore when amplifying floating input sources such as transformers, or ac-coupled sources, there must be a dc path from each input to ground as shown in figures 42a through 42c. refer to the instrumentation amplifier application guide (free from analog devices) for more information regard- ing in amp applications. v out 7 +v s ? s AD621 ?input + input load to power supply ground reference 2 3 4 5 6 figure 42a. ground returns for bias currents when using transformer input coupling v out 7 +v s ? s AD621 ?input + input load to power supply ground reference 2 3 4 5 6 figure 42b. ground returns for bias currents when using a thermocouple input 100k w v out 7 +v s ? s AD621 ?input + input load to power supply ground reference 2 3 4 5 6 100k w figure 42c. ground returns for bias currents when using ac input coupling
AD621 rev. a C16C outline dimensions dimensions shown in inches and (mm). plastic dip (n-8) package 0.125 (3.18) min 0.165 0.01 (4.19 0.25) 0.39 (9.91) max 0.25 (6.35) 4 5 8 1 0.035 0.01 (0.89 0.25) 0.018 0.003 (0.46 0.08) 0.30 (7.62) ref 0 - 15 0.10 (2.54) typ 0.011 0.003 (4.57 0.76) seating plane 0.31 (7.87) 0.18 0.03 (4.57 0.76) 0.033 (0.84) nom cerdip (q-8) package 0.005 (0.13) min 0.055 (1.4) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) max 0.310 (7.87) 0.220 (5.59) 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0 - 15 0.015 (0.38) 0.008 (0.20) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 4 1 5 8 soic (r-8) package 0.181 (4.60) 0.205 (5.20) 0.020 (0.50) 0.045 (1.15) 0.007 (0.18) 0.015 (0.38) 0.100 (2.59) 0.094(2.39) 0.004 (0.10) 0.010 (0.25) 1 4 5 8 0.188 (4.77) 0.198 (5.03) 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.200) 0.014 (0.36) 0.018 (0.46) 0.050 (1.27) typ c1673C24C6/92 printed in u.s.a.

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